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» Automatic microarchitectural pipelining
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HIPEAC
2007
Springer
15 years 3 months ago
Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches
Caches are designed to provide the best tradeoff between access speed and capacity for a set of target applications. Unfortunately, different applications, and even different phas...
Sonia López, Steve Dropsho, David H. Albone...
CGO
2005
IEEE
15 years 3 months ago
Effective Adaptive Computing Environment Management via Dynamic Optimization
To minimize the surging power consumption of microprocessors, adaptive computing environments (ACEs) where microarchitectural resources can be dynamically tuned to match a program...
Shiwen Hu, Madhavi Gopal Valluri, Lizy Kurian John
87
Voted
ISCA
2010
IEEE
236views Hardware» more  ISCA 2010»
15 years 2 months ago
Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors
Next generation tiled microarchitectures are going to be limited by off-chip misses and by on-chip network usage. Furthermore, these platforms will run an heterogeneous mix of ap...
Enric Herrero, José González, Ramon ...
FCCM
2008
IEEE
212views VLSI» more  FCCM 2008»
15 years 4 months ago
Map-reduce as a Programming Model for Custom Computing Machines
The map-reduce model requires users to express their problem in terms of a map function that processes single records in a stream, and a reduce function that merges all mapped out...
Jackson H. C. Yeung, C. C. Tsang, Kuen Hung Tsoi, ...
EGC
2005
Springer
15 years 3 months ago
Statistical Modeling and Segmentation in Cardiac MRI Using a Grid Computing Approach
Abstract. Grid technology is widely emerging as a solution for wide-spread applicability of computerized analysis and processing procedures in biomedical sciences. In this paper we...
Sebastián Ordas, Hans C. van Assen, Loic Bo...