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TCAD
1998
114views more  TCAD 1998»
14 years 9 months ago
Behavioral optimization using the manipulation of timing constraints
— We introduce a transformation, named rephasing, that manipulates the timing parameters in control-data-flow graphs (CDFG’s) during the high-level synthesis of data-pathinten...
Miodrag Potkonjak, Mani B. Srivastava
ASPDAC
2006
ACM
148views Hardware» more  ASPDAC 2006»
15 years 1 months ago
TAPHS: thermal-aware unified physical-level and high-level synthesis
Thermal effects are becoming increasingly important during integrated circuit design. Thermal characteristics influence reliability, power consumption, cooling costs, and performan...
Zhenyu (Peter) Gu, Yonghong Yang, Jia Wang, Robert...
DAC
2006
ACM
15 years 10 months ago
Design space exploration using time and resource duality with the ant colony optimization
Design space exploration during high level synthesis is often conducted through ad-hoc probing of the solution space using some scheduling algorithm. This is not only time consumi...
Gang Wang, Wenrui Gong, Brian DeRenzi, Ryan Kastne...
DAC
2008
ACM
14 years 11 months ago
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
Min Ni, Seda Ogrenci Memik
SAC
2008
ACM
14 years 9 months ago
Towards a model-driven engineering approach for developing embedded hard real-time software
Model-Driven Engineering (MDE) has been advocated as an effective way to deal with today's software complexity. MDE can be seen as an integrative approach combining existing ...
Fabiano Cruz, Raimundo S. Barreto, Lucas Cordeiro