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HPCA
2001
IEEE
16 years 1 days ago
Automatically Mapping Code on an Intelligent Memory Architecture
This paper presents an algorithm to automatically map code on a generic intelligent memory system that consists of a host processor and a simpler memory processor. To achieve high...
Jaejin Lee, Yan Solihin, Josep Torrellas
DAGSTUHL
2007
15 years 1 months ago
Some Experiments on Tiling Loop Programs for Shared-Memory Multicore Architectures
The model-based transformation of loop programs is a way of detecting fine-grained parallelism in sequential programs. One of the challenges is to agglomerate the parallelism to a...
Armin Größlinger
ARCS
2009
Springer
15 years 6 months ago
Evaluating CMPs and Their Memory Architecture
Abstract. Many-core processor architectures require scalable solutions that reflect the locality and power constraints of future generations of technology. This paper presents a CM...
Chris R. Jesshope, Mike Lankamp, Li Zhang
DATE
2006
IEEE
202views Hardware» more  DATE 2006»
15 years 5 months ago
Automatic systemC design configuration for a faster evaluation of different partitioning alternatives
In this paper we present a methodology that is based on SystemC [1] for rapid prototyping to greatly enhance and accelerate the exploration of complex systems to optimize the syst...
Nico Bannow, Karsten Haug, Wolfgang Rosenstiel
CODES
1998
IEEE
15 years 4 months ago
Domain-specific interface generation from dataflow specifications
In this paper, the problem of automatically mapping large-grain dataflow programs onto heterogeneous hardware/softwarearchitectures is treated. Starting with a given hardware/soft...
Michael Eisenring, Jürgen Teich