2585 search results - page 455 / 517 » Automating Coherent Logic |
84
Voted
DAC
2009
ACM
16 years 1 months ago
2009
ACM
State elements are increasingly vulnerable to soft errors due to their decreasing size, and the fact that latched errors cannot be completely eliminated by electrical or timing ma...
111
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DAC
2009
ACM
16 years 1 months ago
2009
ACM
Continuously shrinking feature sizes result in an increasing susceptibility of circuits to transient faults, e.g. due to environmental radiation. Approaches to implement fault tol...
106
Voted
DAC
2008
ACM
16 years 1 months ago
2008
ACM
Extensive software-based simulation continues to be the mainstream methodology for functional verification of designs. To optimize the use of limited simulation resources, coverag...
DAC
2008
ACM
16 years 1 months ago
2008
ACM
Modern CMOS manufacturing processes have significant variability, which necessitates guard banding to achieve reasonable yield. We study an FPGA architecture with a dual voltage s...
102
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DAC
2008
ACM
16 years 1 months ago
2008
ACM
This paper introduces an accurate and efficient electrical analysis of logic gates modeled as Multiple Voltage Threshold Models (MVTM) loaded by the associated interconnect. MVTMs...