The capability of performing architectural exploration has become essential for embedded microprocessor design in System-On-Chip. While many retargetable instruction set (ISA) sim...
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...
This paper presents a unifying framework for the modeling of asynchronous pipeline circuits. A pipeline protocol is captured in a graph-based model which defines the partial order...
Since performance on FPGAs is dominated by the routing architecture rather than wirelength, we propose a new architecture-aware approach to initial FPGA placement that models the ...
Padmini Gopalakrishnan, Xin Li, Lawrence T. Pilegg...
Both technology mapping and circuit clustering have a large impact on FPGA designs in terms of circuit performance, area, and power dissipation. Existing FPGA design flows carry o...