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DAC
2002
ACM
16 years 5 months ago
A general probabilistic framework for worst case timing analysis
CT The traditional approach to worst-case static-timing analysis is becoming unacceptably conservative due to an ever-increasing number of circuit and process effects. We propose a...
Michael Orshansky, Kurt Keutzer
DAC
2002
ACM
16 years 5 months ago
Deriving a simulation input generator and a coverage metric from a formal specification
This paper presents novel uses of functional interface specifications for verifying RTL designs. We demonstrate how a simulation environment, a correctness checker, and a function...
Kanna Shimizu, David L. Dill
DAC
2003
ACM
16 years 5 months ago
Compiler-generated communication for pipelined FPGA applications
In this paper, we describe a set of compiler analyses and an implementation that automatically map a sequential and un-annotated C program into a pipelined implementation, targete...
Heidi E. Ziegler, Mary W. Hall, Pedro C. Diniz
DAC
2004
ACM
16 years 5 months ago
System design for DSP applications in transaction level modeling paradigm
In this paper, we systematically define three transaction level TLMs), which reside at different levels of abstraction between the functional and the implementation model of a DSP...
Abhijit K. Deb, Axel Jantsch, Johnny Öberg
DAC
2004
ACM
16 years 5 months ago
Accurate pre-layout estimation of standard cell characteristics
With the advent of deep-submicron technologies, it has become essential to model the impact of physical/layout effects up front in all design flows [1]. The effect of layout paras...
Hiroaki Yoshida, Kaushik De, Vamsi Boppana