22 search results - page 1 / 5 » Automation of IP Core Interface Generation for Reconfigurabl... |
FPL
2006
Springer
13 years 10 months ago
2006
Springer
Pre-designed IP cores for FPGAs represent a huge intellectual and financial wealth that must be leveraged by any high-level tool targeting reconfigurable platforms. In this paper ...
ICCD
2006
IEEE
14 years 3 months ago
2006
IEEE
By integrating one or more (hard or soft) CPU core on the chip, new generation platform FPGAs have become configurable systems on a chip (CSoC) that support a combined software an...
FPL
2004
Springer
13 years 11 months ago
2004
Springer
Complex SoC and platform-based designs require integration of configurable IP cores from multiple sources. Even automatic compilation flows from a high-level description to HW/SW s...
VLSID
2004
IEEE
14 years 6 months ago
2004
IEEE
System-on-Chip (SoC) design methodologies rely heavily on reuse of intellectual property (IP) blocks. IP reuse is a labour intensive and time consuming process as IP blocks often ...
DAC
2000
ACM
14 years 7 months ago
2000
ACM
In this paper, we present a case study for the design, programming and usage of a reconfigurable system-on-chip, MorphoSys, which is targeted at computation-intensive applications...