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ICPADS
2006
IEEE
15 years 8 months ago
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edw...
IPPS
2006
IEEE
15 years 8 months ago
MegaProto/E: power-aware high-performance cluster with commodity technology
In our research project named “Mega-Scale Computing Based on Low-Power Technology and Workload Modeling”, we have been developing a prototype cluster not based on ASIC or FPGA...
Taisuke Boku, Mitsuhisa Sato, Daisuke Takahashi, H...
PODC
2011
ACM
14 years 4 months ago
Robust network supercomputing without centralized control
Internet supercomputing is becoming an increasingly popular means for harnessing the power of a vast number of interconnected computers. This comes at a cost substantially lower t...
Seda Davtyan, Kishori M. Konwar, Alexander A. Shva...
SAC
2011
ACM
14 years 4 months ago
Type harvesting: a practical approach to obtaining typing information in dynamic programming languages
Dynamically typed programming languages are powerful tools for rapid software development. However, there are scenarios that would benefit from actual type information being avai...
Michael Haupt, Michael Perscheid, Robert Hirschfel...
DATE
2010
IEEE
192views Hardware» more  DATE 2010»
15 years 7 months ago
PhoenixSim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks
—Recent developments have shown the possibility of leveraging silicon nanophotonic technologies for chip-scale interconnection fabrics that deliver high bandwidth and power effi...
Johnnie Chan, Gilbert Hendry, Aleksandr Biberman, ...