5 search results - page 1 / 1 » Avoiding the WCET Overestimation on LRU Instruction Cache |
103
Voted
RTCSA
2008
IEEE
15 years 10 months ago
2008
IEEE
149
Voted
CODES
2007
IEEE
15 years 10 months ago
2007
IEEE
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
176
Voted
RTAS
1996
IEEE
15 years 7 months ago
1996
IEEE
Recent progress in worst case timing analysis of programs has made it possible to perform accurate timing analysis of pipelined execution and instruction caching, which is necessa...
119
Voted
ATVA
2004
Springer
15 years 9 months ago
2004
Springer
nded Abstract – Oleg Parshin∗ Abdur Rakib† Stephan Thesing∗ Reinhard Wilhelm∗ The precise determination of worst-case execution times (WCETs) for programs is mostly bein...
132
Voted
ECRTS
2008
IEEE
15 years 10 months ago
2008
IEEE
Procedure Positioning is a well known compiler optimization aiming at the improvement of the instruction cache behavior. A contiguous mapping of procedures calling each other freq...