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» BASE: Using Abstraction to Improve Fault Tolerance
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DSD
2005
IEEE
105views Hardware» more  DSD 2005»
15 years 3 months ago
Improved Fault Emulation for Synchronous Sequential Circuits
Current paper presents new alternatives for accelerating the task of fault simulation for sequential circuits by hardware emulation on FPGA. Fault simulation is an important subta...
Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, R...
AICCSA
2006
IEEE
137views Hardware» more  AICCSA 2006»
15 years 3 months ago
Modeling Redundancy: Quantitative and Qualitative Models
Redundancy is a system property that generally refers to duplication of state information or system function. While redundancy is usually investigated in the context of fault tole...
Ali Mili, Lan Wu, Frederick T. Sheldon, Mark Shere...
91
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HPCA
2009
IEEE
15 years 10 months ago
Accurate microarchitecture-level fault modeling for studying hardware faults
Decreasing hardware reliability is expected to impede the exploitation of increasing integration projected by Moore's Law. There is much ongoing research on efficient fault t...
Man-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu...
ARCS
2008
Springer
14 years 11 months ago
Topology-Aware Replica Placement in Fault-Tolerant Embedded Networks
Application details uncertain at design time as well as tolerance against permanent resource defects demand flexibility and redundancy. In this context, we present a strategy for p...
Thilo Streichert, Michael Glaß, Rolf Wanka, ...
DSN
2005
IEEE
15 years 3 months ago
A Framework for Node-Level Fault Tolerance in Distributed Real-Time Systems
This paper describes a framework for achieving node-level fault tolerance (NLFT) in distributed realtime systems. The objective of NLFT is to mask errors at the node level in orde...
Joakim Aidemark, Peter Folkesson, Johan Karlsson