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» BDD-based synthesis of reversible logic for large functions
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ASPDAC
2004
ACM
126views Hardware» more  ASPDAC 2004»
15 years 7 months ago
High-level area and power-up current estimation considering rich cell library
— Reducing the ever-growing leakage power is critical to power efficient designs. Leakage reduction techniques such as power-gating using sleep transistor insertion introduces la...
Fei Li, Lei He, Joseph M. Basile, Rakesh J. Patel,...
ISCAS
2006
IEEE
94views Hardware» more  ISCAS 2006»
15 years 7 months ago
On the sensitivity of BDDs with respect to path-related objective functions
— Reduced ordered Binary Decision Diagrams (BDDs) are a data structure for efficient representation and manipulation of Boolean functions. They are frequently used in logic synt...
Rüdiger Ebendt, Rolf Drechsler
DAC
1994
ACM
15 years 5 months ago
Optimum Functional Decomposition Using Encoding
In this paper, we revisit the classical problem of functional decomposition [1, 2] that arises so often in logic synthesis. One basic problem that has remained largely unaddressed...
Rajeev Murgai, Robert K. Brayton, Alberto L. Sangi...
119
Voted
DAC
2007
ACM
16 years 2 months ago
Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits
Despite the impressive progress of logic synthesis in the past decade, finding the best architecture for a given circuit still remains an open problem and largely unsolved. In mos...
Ajay K. Verma, Philip Brisk, Paolo Ienne
96
Voted
DAC
2003
ACM
16 years 2 months ago
Large-scale SOP minimization using decomposition and functional properties
In some cases, minimum Sum-Of-Products (SOP) expressions of Boolean functions can be derived by detecting decomposition and observing the functional properties such as unateness, ...
Alan Mishchenko, Tsutomu Sasao