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ISCA
2006
IEEE
131views Hardware» more  ISCA 2006»
15 years 11 months ago
Reducing Startup Time in Co-Designed Virtual Machines
A Co-Designed Virtual Machine allows designers to implement a processor via a combination of hardware and software. Dynamic binary translation converts code written for a conventi...
Shiliang Hu, James E. Smith
GECCO
2007
Springer
192views Optimization» more  GECCO 2007»
15 years 11 months ago
Analysis of noisy time-series signals with GA involving viral infection with tropism
In this paper we report on a study in which genetic algorithms are applied to the analysis of noisy time-series signals, which is related to the problem of analyzing the motion ch...
Yuji Sato, Yuta Yasuda, Ryuji Goto
ISPASS
2003
IEEE
15 years 10 months ago
Interplay of energy and performance for disk arrays running transaction processing workloads
The growth of business enterprises and the emergence of the Internet as a medium for data processing has led to a proliferation of applications that are server-centric. The power ...
Sudhanva Gurumurthi, Jianyong Zhang, Anand Sivasub...
GECCO
2007
Springer
168views Optimization» more  GECCO 2007»
15 years 11 months ago
Evolutionary benefits of evolvable component integration
A system composed of multiple interacting components is capable of responding to contextual information and producing a higher range of non-linear responses to stimuli compared to...
David Malkin, R. Beau Lotto
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DATE
2006
IEEE
151views Hardware» more  DATE 2006»
15 years 11 months ago
40Gbps de-layered silicon protocol engine for TCP record
We present a de-layered protocol engine for termination of 40Gbps TCP connections using a reconfigurable FPGA silicon platform. This protocol engine is designed for a planned att...
H. Shrikumar