819 search results - page 152 / 164 » BSN Simulator: Optimizing Application Using System Level Sim... |
133
click to vote
CODES
2005
IEEE
15 years 10 months ago
2005
IEEE
In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic channels. We introduce a novel power-smart system-on-chip architecture that provid...
182
click to vote
DAC
2006
ACM
15 years 6 months ago
2006
ACM
With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor SystemOn-Chip (MPSoC) architectures have become widespread. T...
137
click to vote
ISCA
2009
IEEE
15 years 11 months ago
2009
IEEE
Analysis of technology and application trends reveals a growing imbalance in the peak compute-to-memory-capacity ratio for future servers. At the same time, the fraction contribut...
195
click to vote
HIPEAC
2011
Springer
14 years 4 months ago
2011
Springer
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
148
click to vote
MOBICOM
2004
ACM
15 years 10 months ago
2004
ACM
Topology control algorithms usually reduce the number of links in a wireless network, which in turn decreases the degree of connectivity. The resulting network topology is more su...