819 search results - page 30 / 164 » BSN Simulator: Optimizing Application Using System Level Sim... |
IPPS
1997
IEEE
15 years 4 months ago
1997
IEEE
Several optimizations to the Time Warp synchronization protocol for parallel discrete event simulation have been proposed and studied. Many of these optimizations have included so...
112
click to vote
ICPPW
2008
IEEE
15 years 6 months ago
2008
IEEE
Chip multiprocessors (CMP) are widely used for high performance computing. Further, these CMPs are being configured in a hierarchical manner to compose a node in a cluster system....
AINA
2007
IEEE
15 years 6 months ago
2007
IEEE
Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processor cores on the same chip. Chip-multiprocessor...
129
click to vote
CASES
2003
ACM
2003
ACM
A hierarchical approach for energy efficient application design using heterogeneous embedded systems
15 years 3 months ago
Several features such as reconfiguration, voltage and frequency scaling, low-power operating states, duty-cycling, etc. are exploited for latency and energy efficient application ...
BMCBI
2006
14 years 12 months ago
2006
Background: Microarray technologies have become common tools in biological research. As a result, a need for effective computational methods for data analysis has emerged. Numerou...