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CODES
2004
IEEE
15 years 8 months ago
Fast exploration of bus-based on-chip communication architectures
As a result of improvements in process technology, more and more components are being integrated into a single System-on-Chip (SoC) design. Communication between these components ...
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
ICCS
2001
Springer
15 years 9 months ago
Optimizing Sparse Matrix Computations for Register Reuse in SPARSITY
Abstract. Sparse matrix-vector multiplication is an important computational kernel that tends to perform poorly on modern processors, largely because of its high ratio of memory op...
Eun-Jin Im, Katherine A. Yelick
ECBS
2006
IEEE
158views Hardware» more  ECBS 2006»
15 years 11 months ago
Automated Translation of C/C++ Models into a Synchronous Formalism
For complex systems that are reusing intellectual property components, functional and compositional design correctness are an important part of the design process. Common system l...
Hamoudi Kalla, Jean-Pierre Talpin, David Berner, L...
146
Voted
ISLPED
2003
ACM
115views Hardware» more  ISLPED 2003»
15 years 10 months ago
Reducing energy and delay using efficient victim caches
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
Gokhan Memik, Glenn Reinman, William H. Mangione-S...
HVEI
2010
15 years 3 months ago
No-reference image quality assessment based on localized gradient statistics: application to JPEG and JPEG2000
This paper presents a novel system that employs an adaptive neural network for the no-reference assessment of perceived quality of JPEG/JPEG2000 coded images. The adaptive neural ...
Hantao Liu, Judith Redi, Hani Alers, Rodolfo Zunin...