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» Balance Testing of Logic Circuits
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DFT
2002
IEEE
121views VLSI» more  DFT 2002»
13 years 11 months ago
Testing Digital Circuits with Constraints
Many digital circuits have constraints on the logic values a set of signal lines can have. In this paper, we present two new techniques for detecting the illegal combinations of l...
Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McC...
ICCAD
2003
IEEE
135views Hardware» more  ICCAD 2003»
13 years 11 months ago
ATPG for Noise-Induced Switch Failures in Domino Logic
Domino circuits have been used in most modern high-performance microprocessor designs because of their high speed, low transistor-count and hazard-free operation. However, with te...
Rahul Kundu, R. D. (Shawn) Blanton
ITC
2003
IEEE
167views Hardware» more  ITC 2003»
13 years 11 months ago
Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk
A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of...
Rahul Kundu, R. D. (Shawn) Blanton
ITC
2003
IEEE
108views Hardware» more  ITC 2003»
13 years 11 months ago
Backplane Test Bus Applications For IEEE STD 1149.1
Prior to the mid 1980s, the dominance of through-hole packaging of integrated circuits (ICs) provided easy access to nearly every pin of every chip on a printed circuit board. Pro...
Clayton Gibbs
ISMVL
1994
IEEE
94views Hardware» more  ISMVL 1994»
13 years 10 months ago
Full Sensitivity and Test Generation for Multiple-Valued Logic Circuits
Elena Dubrova, Dilian Gurov, Jon C. Muzio