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» Balancing power consumption in multiprocessor systems
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HPCA
2009
IEEE
14 years 6 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
ISCA
2009
IEEE
152views Hardware» more  ISCA 2009»
14 years 1 months ago
Scaling the bandwidth wall: challenges in and avenues for CMP scaling
As transistor density continues to grow at an exponential rate in accordance to Moore’s law, the goal for many Chip Multi-Processor (CMP) systems is to scale the number of on-ch...
Brian M. Rogers, Anil Krishna, Gordon B. Bell, Ken...
EUROPAR
2010
Springer
13 years 7 months ago
Optimized Dense Matrix Multiplication on a Many-Core Architecture
Abstract. Traditional parallel programming methodologies for improving performance assume cache-based parallel systems. However, new architectures, like the IBM Cyclops-64 (C64), b...
Elkin Garcia, Ioannis E. Venetis, Rishi Khan, Guan...
TMC
2010
141views more  TMC 2010»
13 years 4 months ago
Energy-Optimal Scheduling with Dynamic Channel Acquisition in Wireless Downlinks
—We consider a wireless base station serving L users through L time-varying channels. It is well known that opportunistic scheduling algorithms with full channel state informatio...
Chih-Ping Li, Michael J. Neely
INFOCOM
2006
IEEE
14 years 11 days ago
Design Guidelines for Maximizing Lifetime and Avoiding Energy Holes in Sensor Networks with Uniform Distribution and Uniform Rep
— This paper investigates theoretical aspects of the uneven energy depletion phenomenon recently noticed in sink-based wireless sensor networks. We consider uniformly distributed...
Stephan Olariu, Ivan Stojmenovic