Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
As transistor density continues to grow at an exponential rate in accordance to Moore’s law, the goal for many Chip Multi-Processor (CMP) systems is to scale the number of on-ch...
Brian M. Rogers, Anil Krishna, Gordon B. Bell, Ken...
Abstract. Traditional parallel programming methodologies for improving performance assume cache-based parallel systems. However, new architectures, like the IBM Cyclops-64 (C64), b...
Elkin Garcia, Ioannis E. Venetis, Rishi Khan, Guan...
—We consider a wireless base station serving L users through L time-varying channels. It is well known that opportunistic scheduling algorithms with full channel state informatio...
— This paper investigates theoretical aspects of the uneven energy depletion phenomenon recently noticed in sink-based wireless sensor networks. We consider uniformly distributed...