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ASAP
2005
IEEE
169views Hardware» more  ASAP 2005»
15 years 3 months ago
Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
Grigoris Dimitroulakos, Michalis D. Galanis, Costa...
ISCA
1996
IEEE
99views Hardware» more  ISCA 1996»
15 years 1 months ago
High-Bandwidth Address Translation for Multiple-Issue Processors
In an effort to push the envelope of system performance, microprocessor designs are continually exploiting higher levels of instruction-level parallelism, resulting in increasing ...
Todd M. Austin, Gurindar S. Sohi
WWW
2001
ACM
15 years 10 months ago
Map adaptation for users of mobile systems
Display characteristics, network Quality of Service, and the user's current task all exhibit a wide range of variation when users interact with mobile and ubiquitous devices....
Dan Chalmers, Morris Sloman, Naranker Dulay
81
Voted
TWC
2008
136views more  TWC 2008»
14 years 9 months ago
On Antijamming in General CDMA Systems-Part II: Antijamming Performance of Coded Multicarrier Frequency-Hopping Spread Spectrum
In the first part of the paper, the capacity of a general multiuser code division multiple access (CDMA) jamming channel was analyzed for noncooperative and cooperative users in up...
Reza Nikjah, Norman C. Beaulieu
EUROPAR
2000
Springer
15 years 1 months ago
Use of Performance Technology for the Management of Distributed Systems
This paper describes a toolset, PACE, that provides detailed predictive performance information throughout the implementation and execution stages of an application. It is structur...
Darren J. Kerbyson, John S. Harper, Efstathios Pap...