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ISVLSI
2002
IEEE
109views VLSI» more  ISVLSI 2002»
13 years 11 months ago
A Network on Chip Architecture and Design Methodology
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnn...
ICCAD
2006
IEEE
177views Hardware» more  ICCAD 2006»
14 years 3 months ago
Application-specific customization of parameterized FPGA soft-core processors
Soft-core microprocessors mapped onto field-programmable gate arrays (FPGAs) represent an increasingly common embedded software implementation option. Modern FPGA soft-cores are p...
David Sheldon, Rakesh Kumar, Roman L. Lysecky, Fra...
DAC
2004
ACM
13 years 10 months ago
An SoC design methodology using FPGAs and embedded microprocessors
In System on Chip (SoC) design, growing design complexity has esigners to start designs at higher abstraction levels. This paper proposes an SoC design methodology that makes full...
Nobuyuki Ohba, Kohji Takano
ICASSP
2010
IEEE
13 years 4 months ago
A distributed psycho-visually motivated Canny edge detector
This paper proposes a distributed Canny edge detection algorithm which can be mapped onto multi-core architectures for high throughput applications. In contrast to the conventiona...
Srenivas Varadarajan, Chaitali Chakrabarti, Lina J...
SAMOS
2009
Springer
14 years 23 days ago
Experiences with Cell-BE and GPU for Tomography
Tomography is a powerful technique for three-dimensional imaging, that deals with image reconstruction from a series of projection images, acquired along a range of viewing directi...
Sander van der Maar, Kees Joost Batenburg, Jan Sij...