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ISSS
2002
IEEE
130views Hardware» more  ISSS 2002»
15 years 9 months ago
System-Level Modeling of a Network Switch SoC
We present the modeling of the high-level design of a next generation network switch from the perspective of a ComputerAided Design (CAD) team within the larger context of a desig...
Andrew S. Cassidy, Christopher P. Andrews, Donald ...
KBSE
2002
IEEE
15 years 9 months ago
SeDiTeC - Testing Based on Sequence Diagrams
In this paper we present a concept for automated testing of object-oriented applications and a tool called SeDiTeC that implements these concepts for Java applications. SeDiTeC us...
Falk Fraikin, Thomas Leonhardt
VISUALIZATION
2002
IEEE
15 years 9 months ago
GeneVis: Visualization Tools for Genetic Regulatory Network Dynamics
GeneVis provides a visual environment for exploring the dynamics of genetic regulatory networks. At present time, genetic regulation is the focus of intensive research worldwide, ...
Charles A. H. Baker, M. Sheelagh T. Carpendale, Pr...
GECCO
2010
Springer
194views Optimization» more  GECCO 2010»
15 years 8 months ago
Fitting multi-planet transit models to photometric time-data series by evolution strategies
In this paper we present the application of an evolution strategy to the problem of detecting multi-planet transit events in photometric time-data series. Planetary transits occur...
Andreas M. Chwatal, Günther R. Raidl, Michael...
GLVLSI
2010
IEEE
310views VLSI» more  GLVLSI 2010»
15 years 8 months ago
Graphene tunneling FET and its applications in low-power circuit design
Graphene nanoribbon tunneling FETs (GNR TFETs) are promising devices for post-CMOS low-power applications because of the low subthreshold swing, high Ion/Ioff, and potential for l...
Xuebei Yang, Jyotsna Chauhan, Jing Guo, Kartik Moh...