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ISCA
2011
IEEE
313views Hardware» more  ISCA 2011»
14 years 1 months ago
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay ...
WWW
2010
ACM
15 years 5 months ago
Malicious interface design: exploiting the user
In an ideal world, interface design is the art and science of helping users accomplish tasks in a timely, efficient, and pleasurable manner. This paper studies the inverse situati...
Gregory J. Conti, Edward Sobiesk
ANCS
2011
ACM
13 years 10 months ago
ReClick - A Modular Dataplane Design Framework for FPGA-Based Network Virtualization
Network virtualization has emerged as a powerful technique to deploy novel services and experimental protocols over shared network infrastructures. Although recent research has hi...
Deepak Unnikrishnan, Justin Lu, Lixin Gao, Russell...
MICRO
2008
IEEE
137views Hardware» more  MICRO 2008»
15 years 4 months ago
Tradeoffs in designing accelerator architectures for visual computing
Visualization, interaction, and simulation (VIS) constitute a class of applications that is growing in importance. This class includes applications such as graphics rendering, vid...
Aqeel Mahesri, Daniel R. Johnson, Neal C. Crago, S...
SAS
2007
Springer
108views Formal Methods» more  SAS 2007»
15 years 4 months ago
Programming Language Design and Analysis Motivated by Hardware Evolution
Abstract. Silicon chip design has passed a threshold whereby exponentially increasing transistor density (Moore’s Law) no longer translates into increased processing power for si...
Alan Mycroft