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DAC
2009
ACM
16 years 4 months ago
Optimal static WCET-aware scratchpad allocation of program code
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access will result in a definite cache hit or miss. This unpredictabilit...
Heiko Falk, Jan C. Kleinsorge
113
Voted
GLVLSI
2008
IEEE
112views VLSI» more  GLVLSI 2008»
15 years 10 months ago
Instruction cache leakage reduction by changing register operands and using asymmetric sram cells
Share of leakage in cache memories is increasing with technology scaling. Studies show that most stored bits in instruction caches are zero, and hence, asymmetric SRAM cells which...
Maziar Goudarzi, Tohru Ishihara
DATE
2005
IEEE
143views Hardware» more  DATE 2005»
15 years 9 months ago
galsC: A Language for Event-Driven Embedded Systems
— We introduce galsC, a language designed for programming event-driven embedded systems such as sensor networks. galsC implements the TinyGALS programming model. At the local lev...
Elaine Cheong, Jie Liu
SFM
2005
Springer
243views Formal Methods» more  SFM 2005»
15 years 9 months ago
Hermes: Agent-Based Middleware for Mobile Computing
Hermes is a middleware system for design and execution of activity-based applications in distributed environments. It supports mobile computation as an application implementation s...
Flavio Corradini, Emanuela Merelli
117
Voted
ISCA
1998
IEEE
151views Hardware» more  ISCA 1998»
15 years 7 months ago
Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture
Explicitly Parallel Instruction Computing (EPIC) architectures require the compiler to express program instruction level parallelism directly to the hardware. EPIC techniques whic...
David I. August, Daniel A. Connors, Scott A. Mahlk...