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DAC
2003
ACM
16 years 4 months ago
Clock-tree power optimization based on RTL clock-gating
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...
Monica Donno, Alessandro Ivaldi, Luca Benini, Enri...
149
Voted
SBCCI
2006
ACM
200views VLSI» more  SBCCI 2006»
15 years 9 months ago
REDEFIS: a system with a redefinable instruction set processor
The growing complexity and production cost of processor-based systems have imposed big constraints in SoC design of new systems. GPPs and ASICs are unable to fit the tight perform...
Victor M. Goulart Ferreira, Lovic Gauthier, Takayu...
FCCM
2002
IEEE
133views VLSI» more  FCCM 2002»
15 years 8 months ago
Reconfigurable Shape-Adaptive Template Matching Architectures
This paper presents three reconfigurable computing approaches for a Shape-Adaptive Template Matching (SA-TM) method to retrieve arbitrarily shaped objects within images or video f...
Jörn Gause, Peter Y. K. Cheung, Wayne Luk
252
Voted
TCAD
2011
14 years 10 months ago
High-Level Synthesis for FPGAs: From Prototyping to Deployment
—Escalating system-on-chip design complexity is the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early...
Jason Cong, Bin Liu, Stephen Neuendorffer, Juanjo ...
86
Voted
ISCAS
2006
IEEE
114views Hardware» more  ISCAS 2006»
15 years 9 months ago
System for deposition and characterization of polypyrrole/gold bilayer hinges
— We report on a custom designed system for the deposition and characterization of polypyrrole bilayer actuators. Unlike conventional commercial electrochemical cells and potenti...
Edward Choi, Yingkai Liu, Elisabeth Smela, Andreas...