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LCTRTS
2001
Springer
15 years 8 months ago
Middleware For Building Adaptive Systems Via Configuration
1 COTS (commercial off-the-shelf) devices are capable of executing powerful, distributed algorithms. Very large, adaptive systems can be created by simply integrating these devices...
Sanjai Narain, Ravichander Vaidyanathan, Stanley M...
137
Voted
ISCA
1995
IEEE
110views Hardware» more  ISCA 1995»
15 years 7 months ago
Optimization of Instruction Fetch Mechanisms for High Issue Rates
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...
Thomas M. Conte, Kishore N. Menezes, Patrick M. Mi...
MAM
2007
157views more  MAM 2007»
15 years 3 months ago
Executing large algorithms on low-capacity FPGAs using flowpath partitioning and runtime reconfiguration
This paper describes a new method of executing a software program on an FPGA for embedded systems. Rather than combine reconfigurable logic with a microprocessor core, this method...
Darrin M. Hanna, Michael DuChene
DAC
2004
ACM
16 years 4 months ago
Data compression for improving SPM behavior
Scratch-pad memories (SPMs) enable fast access to time-critical data. While prior research studied both static and dynamic SPM management strategies, not being able to keep all ho...
Ozcan Ozturk, Mahmut T. Kandemir, I. Demirkiran, G...
231
Voted
POPL
2008
ACM
16 years 3 months ago
Formal verification of translation validators: a case study on instruction scheduling optimizations
Translation validation consists of transforming a program and a posteriori validating it in order to detect a modification of its semantics. This approach can be used in a verifie...
Jean-Baptiste Tristan, Xavier Leroy