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TC
1998
15 years 6 months ago
Using Decision Diagrams to Design ULMs for FPGAs
—Many modern Field Programmable Logic Arrays (FPGAs) use lookup table (LUT) logic blocks which can be programmed to realize any function of a fixed number of inputs. It is possib...
Zeljko Zilic, Zvonko G. Vranesic
JSAC
2007
63views more  JSAC 2007»
15 years 6 months ago
A new survivable mapping problem in IP-over-WDM networks
— We introduce a new version of the widely studied survivable mapping problem in IP-over-WDM networks. The new problem allows augmenting the given logical topology and is describ...
Chang Liu, Lu Ruan
SEFM
2005
IEEE
16 years 2 days ago
Description Logics for Shape Analysis
Verification of programs requires reasoning about sets of program states. In case of programs manipulating pointers, program states are pointer graphs. Verification of such prog...
Lilia Georgieva, Patrick Maier
BIRTHDAY
2005
Springer
16 years 1 days ago
a-logic
We present an extension of first-order predicate logic with a novel predicate ‘at t’ meaning intuitively “this term is a variable symbol”. We give simple sequent proof-ru...
Murdoch Gabbay, Michael Gabbay
CONCUR
2005
Springer
16 years 1 days ago
A New Modality for Almost Everywhere Properties in Timed Automata
The context of this study is timed temporal logics for timed automata. In this paper, we propose an extension of the classical logic TCTL with a new Until modality, called “Until...
Houda Bel Mokadem, Béatrice Bérard, ...