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DSD
2010
IEEE
112views Hardware» more  DSD 2010»
14 years 8 months ago
Re-NUCA: Boosting CMP Performance Through Block Replication
— Chip Multiprocessor (CMP) systems have become the reference architecture for designing micro-processors, thanks to the improvements in semiconductor nanotechnology that have co...
Pierfrancesco Foglia, Cosimo Antonio Prete, Marco ...
ICS
2010
Tsinghua U.
14 years 8 months ago
Decomposable and responsive power models for multicore processors using performance counters
Abstract—Power modeling based on performance monitoring counters (PMCs) has attracted the interest of many researchers since it become a quick approach to understand and analyse ...
Ramon Bertran, Marc González, Xavier Martor...
IEEECIT
2010
IEEE
14 years 8 months ago
CFCSS without Aliasing for SPARC Architecture
With the increasing popularity of COTS (commercial off the shelf) components and multi-core processor in space and aviation applications, software fault tolerance becomes attracti...
Chao Wang, Zhongchuan Fu, Hongsong Chen, Wei Ba, B...
IFE
2010
161views more  IFE 2010»
14 years 8 months ago
Adaptive estimation and prediction of power and performance in high performance computing
Power consumption has become an increasingly important constraint in high-performancecomputing systems, shifting the focus from peak performance towards improving power efficiency...
Reza Zamani, Ahmad Afsahi
IJRR
2010
173views more  IJRR 2010»
14 years 8 months ago
Planning and Implementing Trajectories for Autonomous Underwater Vehicles to Track Evolving Ocean Processes Based on Predictions
Path planning and trajectory design for autonomous underwater vehicles (AUVs) is of great importance to the oceanographic research community because automated data collection is b...
Ryan N. Smith, Yi Chao, Peggy Li, David A. Caron, ...
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