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» Benchmark Generation Using Domain Specific Modeling
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DSD
2003
IEEE
138views Hardware» more  DSD 2003»
15 years 3 months ago
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
Network on Chip (NoC) is a new paradigm for designing core based System on Chip which supports high degree of reusability and is scalable. In this paper we describe an efficient t...
Tang Lei, Shashi Kumar
ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
15 years 2 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
SP
1998
IEEE
106views Security Privacy» more  SP 1998»
15 years 2 months ago
Understanding Java Stack Inspection
Current implementations of Java make security decisions by searching the runtime call stack. These systems have attractive security properties, but they have been criticized as be...
Dan S. Wallach, Edward W. Felten
ICDM
2007
IEEE
147views Data Mining» more  ICDM 2007»
15 years 1 months ago
Improving Knowledge Discovery in Document Collections through Combining Text Retrieval and Link Analysis Techniques
In this paper, we present Concept Chain Queries (CCQ), a special case of text mining in document collections focusing on detecting links between two topics across text documents. ...
Wei Jin, Rohini K. Srihari, Hung Hay Ho, Xin Wu
CONCUR
2006
Springer
15 years 1 months ago
Minimization, Learning, and Conformance Testing of Boolean Programs
Boolean programs with recursion are convenient abstractions of sequential imperative programs, and can be represented as recursive state machines (RSMs) or pushdown automata. Motiv...
Viraj Kumar, P. Madhusudan, Mahesh Viswanathan