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HPCA
2008
IEEE
15 years 10 months ago
Uncovering hidden loop level parallelism in sequential applications
As multicore systems become the dominant mainstream computing technology, one of the most difficult challenges the industry faces is the software. Applications with large amounts ...
Hongtao Zhong, Mojtaba Mehrara, Steven A. Lieberma...
CADE
2007
Springer
15 years 10 months ago
Solving Quantified Verification Conditions Using Satisfiability Modulo Theories
Abstract. First order logic provides a convenient formalism for describing a wide variety of verification conditions. Two main approaches to checking such conditions are pure first...
Yeting Ge, Clark Barrett, Cesare Tinelli
EUROSYS
2007
ACM
15 years 6 months ago
Macroprogramming heterogeneous sensor networks using cosmos
In this paper, we present COSMOS, a novel architecture for macroprogramming heterogeneous sensor network systems. Macroprogramming entails aggregate system behavior specification...
Asad Awan, Suresh Jagannathan, Ananth Grama
ICCAD
2008
IEEE
108views Hardware» more  ICCAD 2008»
15 years 6 months ago
FBT: filled buffer technique to reduce code size for VLIW processors
— VLIW processors provide higher performance and better efficiency etc. than RISC processors in specific domains like multimedia applications etc. A disadvantage is the bloated...
Talal Bonny, Jörg Henkel
ASPLOS
2010
ACM
15 years 4 months ago
Request behavior variations
A large number of user requests execute (often concurrently) within a server system. A single request may exhibit fluctuating hardware characteristics (such as instruction comple...
Kai Shen