Sciweavers

441 search results - page 53 / 89
» Benchmarking Technique in E-Business Using the Galileo Metho...
Sort
View
ASPDAC
2004
ACM
113views Hardware» more  ASPDAC 2004»
15 years 3 months ago
Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction
- Minimum area is one of the important objectives in technology mapping for lookup table-based FPGAs. It has been proven that the problem is NP-complete. This paper presents a poly...
Chi-Chou Kao, Yen-Tai Lai
MCS
2000
Springer
15 years 3 months ago
Classifier Instability and Partitioning
Various methods exist for reducing correlation between classifiers in a multiple classifier framework. The expectation is that the composite classifier will exhibit improved perfor...
Terry Windeatt
ICS
1995
Tsinghua U.
15 years 3 months ago
Optimum Modulo Schedules for Minimum Register Requirements
Modulo scheduling is an e cient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirement...
Alexandre E. Eichenberger, Edward S. Davidson, San...
FMCAD
1998
Springer
15 years 4 months ago
Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification
We present a new approach to the verification of hardware systems with data dependencies using temporal logic symbolic model checking. As a benchmark we take Tomasulo's algori...
Sergey Berezin, Armin Biere, Edmund M. Clarke, Yun...
DATE
2009
IEEE
106views Hardware» more  DATE 2009»
15 years 6 months ago
Generation of compact test sets with high defect coverage
Abstract-Multi-detect (N-detect) testing suffers from the drawback that its test length grows linearly with N. We present a new method to generate compact test sets that provide hi...
Xrysovalantis Kavousianos, Krishnendu Chakrabarty