Sciweavers

436 search results - page 73 / 88
» Benchmarking and hardware implementation of JPEG-LS
Sort
View
100
Voted
LCPC
2005
Springer
15 years 7 months ago
Optimizing Packet Accesses for a Domain Specific Language on Network Processors
Programming network processors remains a challenging task since their birth until recently when high-level programming environments for them are emerging. By employing domain speci...
Tao Liu, Xiao-Feng Li, Lixia Liu, Chengyong Wu, Ro...
IWSOC
2003
IEEE
104views Hardware» more  IWSOC 2003»
15 years 7 months ago
Incorporating Pattern Prediction Technique for Energy Efficient Filter Cache Design
: - A filter cache is proposed at a higher level than the L1 (main) cache in the memory hierarchy and is much smaller. The typical size of filter cache is of the order of 512 Bytes...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...
113
Voted
ISSS
2002
IEEE
127views Hardware» more  ISSS 2002»
15 years 6 months ago
Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis
We introduce a new approach, “Dynamic Common Sub-expression Elimination (CSE)”, that dynamically eliminates common sub- expressions based on new opportunities created during s...
Alexandru Nicolau, Nikil D. Dutt, Rajesh Gupta, Ni...
MICRO
2002
IEEE
97views Hardware» more  MICRO 2002»
15 years 6 months ago
Three extensions to register integration
Register integration (or just integration) is a register renaming discipline that implements instruction reuse via physical register sharing. Initially developed to perform squash...
Vlad Petric, Anne Bracy, Amir Roth
105
Voted
HPCA
2000
IEEE
15 years 6 months ago
A Prefetching Technique for Irregular Accesses to Linked Data Structures
Prefetching offers the potential to improve the performance of linked data structure (LDS) traversals. However, previously proposed prefetching methods only work well when there i...
Magnus Karlsson, Fredrik Dahlgren, Per Stenstr&oum...