686 search results - page 30 / 138 » Benchmarking cerebellar control |
73
Voted
MICRO
2006
IEEE
15 years 3 months ago
2006
IEEE
Secure processor architecture enables tamper-proof protection on software that addresses many difficult security problems such as reverse-engineering prevention, trusted computing...
97
Voted
ICTAI
2005
IEEE
15 years 3 months ago
2005
IEEE
In this paper, we study strategies in incremental planning for ordering and grouping subproblems partitioned by the subgoals of a planning problem when each subproblem is solved b...
DFT
2003
IEEE
15 years 3 months ago
2003
IEEE
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
IEEEPACT
2002
IEEE
15 years 2 months ago
2002
IEEE
In this paper, we describe an algorithm and implementation of locality optimizations for architectures with instruction sets such as Intel’s SSE and Motorola’s AltiVec that su...
CGO
2004
IEEE
15 years 1 months ago
2004
IEEE
Operand gating is a technique for improving processor energy efficiency by gating off sections of the data path that are unneeded by short-precision (narrow) operands. A method fo...