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RTSS
1999
IEEE
15 years 4 months ago
Timing Anomalies in Dynamically Scheduled Microprocessors
Previous timing analysis methods have assumed that the worst-case instruction execution time necessarily corresponds to the worst-case behavior. We show that this assumption is wr...
Thomas Lundqvist, Per Stenström
SIGMETRICS
1994
ACM
113views Hardware» more  SIGMETRICS 1994»
15 years 4 months ago
Shade: A Fast Instruction-Set Simulator for Execution Profiling
Shade is an instruction-set simulator and custom trace generator. Application programs are executed and traced under the control of a user-supplied trace analyzer. To reduce commu...
Robert F. Cmelik, David Keppel
DATE
2009
IEEE
123views Hardware» more  DATE 2009»
15 years 3 months ago
Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis
This paper exploits the unique in-field controllability of the device polarity of ambipolar carbon nanotube field effect transistors (CNTFETs) to design a technology library with ...
M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De ...
GLVLSI
2007
IEEE
151views VLSI» more  GLVLSI 2007»
15 years 3 months ago
Hand-in-hand verification of high-level synthesis
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Ma...
FROCOS
2009
Springer
15 years 3 months ago
Efficient Combination of Decision Procedures for MUS Computation
In recent years, the problem of extracting a MUS (Minimal Unsatisfiable Subformula) from an unsatisfiable CNF has received much attention. Indeed, when a Boolean formula is proved ...
Cédric Piette, Youssef Hamadi, Lakhdar Sais