686 search results - page 81 / 138 » Benchmarking cerebellar control |
HPCA
2007
IEEE
16 years 6 days ago
2007
IEEE
Transactional Memory (TM) provides mechanisms that promise to simplify parallel programming by eliminating the need for locks and their associated problems (deadlock, livelock, pr...
HPCA
2004
IEEE
16 years 6 days ago
2004
IEEE
Branch misprediction penalty consists of two components: the time wasted on mis-speculative execution until the mispredicted branch is resolved and the time to restart the pipelin...
102
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OSDI
2008
ACM
16 years 4 days ago
2008
ACM
This paper proposes to develop a system-wide energy consumption model for servers by making use of hardware performance counters and experimental measurements. We develop a real-t...
120
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OSDI
2002
ACM
16 years 4 days ago
2002
ACM
Most general-purpose processors provide support for memory pages of large sizes, called superpages. Superpages enable each entry in the translation lookaside buffer (TLB) to map a...
173
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VLDB
2007
ACM
16 years 2 days ago
2007
ACM
Query generators producing sequences of SQL statements are embedded in many applications. As the execution time of such sequences is often far from optimal, their optimization is ...