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» Benchmarking weak memory models
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172
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ASPLOS
1994
ACM
15 years 7 months ago
Compiler Optimizations for Improving Data Locality
In the past decade, processor speed has become significantly faster than memory speed. Small, fast cache memories are designed to overcome this discrepancy, but they are only effe...
Steve Carr, Kathryn S. McKinley, Chau-Wen Tseng
94
Voted
DAC
2009
ACM
16 years 4 months ago
WCET-aware register allocation based on graph coloring
Current compilers lack precise timing models guiding their built-in optimizations. Hence, compilers apply ad-hoc heuristics during optimization to improve code quality. One of the...
Heiko Falk
132
Voted
ICCD
2001
IEEE
110views Hardware» more  ICCD 2001»
16 years 9 days ago
Low-Energy DSP Code Generation Using a Genetic Algorithm
This paper deals with low-energy code generation for a highly optimized digital signal processor designed for mobile communication applications. We present a genetic algorithm bas...
Markus Lorenz, Rainer Leupers, Peter Marwedel, Tho...
223
Voted
ASIAMS
2009
IEEE
15 years 8 months ago
Evolutionary-Reduced Ordered Binary Decision Diagram
—Reduced ordered binary decision diagram (ROBDD) is a memory-efficient data structure which is used in many applications such as synthesis, digital system, verification, testing ...
Hossein Moeinzadeh, Mehdi Mohammadi, Hossein Pazho...
142
Voted
EUROPAR
2007
Springer
15 years 7 months ago
Efficient Parallel Simulation of Large-Scale Neuronal Networks on Clusters of Multiprocessor Computers
To understand the principles of information processing in the brain, we depend on models with more than 105 neurons and 109 connections. These networks can be described as graphs o...
Hans E. Plesser, Jochen M. Eppler, Abigail Morriso...