317 search results - page 52 / 64 » Benchmarking weak memory models |
WSC
1997
15 years 1 months ago
1997
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
129
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IWOMP
2007
Springer
15 years 5 months ago
2007
Springer
The Cell processor is a heterogeneous multi-core processor with one Power Processing Engine (PPE) core and eight Synergistic Processing Engine (SPE) cores. Each SPE has a directly...
PLDI
2010
ACM
15 years 4 months ago
2010
ACM
Self-adjusting computation provides an evaluation model where computations can respond automatically to modifications to their data by using a mechanism for propagating modifica...
103
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CCGRID
2002
IEEE
15 years 4 months ago
2002
IEEE
Despite the large research efforts in the SW–DSM community, this technology has not yet been adapted widely for significant codes beyond benchmark suites. One of the reasons co...
104
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JUCS
2000
14 years 11 months ago
2000
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...