317 search results - page 59 / 64 » Benchmarking weak memory models |
83
Voted
LOPSTR
2005
Springer
15 years 5 months ago
2005
Springer
Abstract. Several models for context-sensitive analysis of modular programs have been proposed, each with different characteristics and representing different trade-offs. The ad...
112
Voted
HPCA
2011
IEEE
14 years 3 months ago
2011
IEEE
Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization...
CODES
2008
IEEE
15 years 6 months ago
2008
IEEE
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
CODES
2008
IEEE
15 years 6 months ago
2008
IEEE
Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip estate. Simulation, in partic...
SUTC
2008
IEEE
15 years 6 months ago
2008
IEEE
A piece of Hovering Information is a geo-localized information residing in a highly dynamic environment such as a mobile ad hoc network. This information is attached to a geograph...