615 search results - page 46 / 123 » Beta Reduction Constraints |
116
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TCAD
2008
15 years 19 days ago
2008
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
121
Voted
ASPDAC
2012
ACM
13 years 8 months ago
2012
ACM
In this paper, we examine the integration potential and explore the design space of low power thermal reliable on-chip interconnect synthesis featuring nanophotonics Wavelength Di...
95
Voted
DAC
2004
ACM
16 years 1 months ago
2004
ACM
Logic duplication, a commonly used synthesis technique to remove trapped inverters in reconvergent paths of Domino circuits, incurs high area and power penalties. In this paper, w...
99
Voted
ICCAD
2006
IEEE
15 years 9 months ago
2006
IEEE
Power consumption is a crucial concern in nanometer chip design. Researchers have shown that multiple supply voltage (MSV) is an effective method for power consumption reduction....
85
Voted
ATS
2009
IEEE
15 years 7 months ago
2009
IEEE
High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to faci...