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116
Voted
ICCD
2007
IEEE
205views Hardware» more  ICCD 2007»
15 years 9 months ago
Hardware libraries: An architecture for economic acceleration in soft multi-core environments
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
David Meisner, Sherief Reda
86
Voted
ICCAD
2003
IEEE
124views Hardware» more  ICCAD 2003»
15 years 9 months ago
Gradual Relaxation Techniques with Applications to Behavioral Synthesis
Heuristics are widely used for solving computational intractable synthesis problems. However, until now, there has been limited effort to systematically develop heuristics that ca...
Zhiru Zhang, Yiping Fan, Miodrag Potkonjak, Jason ...
96
Voted
ISQED
2010
IEEE
177views Hardware» more  ISQED 2010»
15 years 7 months ago
Multi-corner, energy-delay optimized, NBTI-aware flip-flop design
With the CMOS transistors being scaled to sub 45nm and lower, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging pr...
Hamed Abrishami, Safar Hatami, Massoud Pedram
SAC
2009
ACM
15 years 7 months ago
Flexible self-healing gradients
Self-healing gradients are distributed estimates of the distance from each device in a network to the nearest device designated as a source, and are used in many pervasive computi...
Jacob Beal
107
Voted
GLVLSI
2009
IEEE
122views VLSI» more  GLVLSI 2009»
15 years 7 months ago
Enhancing SAT-based sequential depth computation by pruning search space
The sequential depth determines the completeness of bounded model checking in design verification. Recently, a SATbased method is proposed to compute the sequential depth of a de...
Yung-Chih Chen, Chun-Yao Wang