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DATE
1999
IEEE
81views Hardware» more  DATE 1999»
15 years 2 months ago
A Power Estimation Model for High-Speed CMOS A/D Converters
Power estimation is important for system-level exploration and trade-off analysis of VLSI systems. A power estimator for high-speed analog to digital converters that exploits info...
Erik Lauwers, Georges G. E. Gielen
58
Voted
ASPDAC
2007
ACM
96views Hardware» more  ASPDAC 2007»
15 years 1 months ago
A Novel Performance-Driven Topology Design Algorithm
This paper presents a very efficient algorithm for performance-driven topology design for interconnects. Given a net, it first generates A-tree1 topology using table lookup and net...
Min Pan, Chris C. N. Chu, Priyadarshan Patra
ICCD
2011
IEEE
296views Hardware» more  ICCD 2011»
13 years 9 months ago
DPPC: Dynamic power partitioning and capping in chip multiprocessors
—A key challenge in chip multiprocessor (CMP) design is to optimize the performance within a power budget limited by the CMP’s cooling, packaging, and power supply capacities. ...
Kai Ma, Xiaorui Wang, Yefu Wang
CASES
2003
ACM
15 years 2 months ago
Power efficient encoding techniques for off-chip data buses
Reducing the power consumption of computing devices has gained a lot of attention recently. Many research works have focused on reducing power consumption in the off-chip buses as...
Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Wa...
ASPDAC
2004
ACM
96views Hardware» more  ASPDAC 2004»
15 years 3 months ago
Register binding and port assignment for multiplexer optimization
- Data path connection elements, such as multiplexers, consume a significant amount of area on a VLSI chip, especially for FPGA designs. Multiplexer optimization is a difficult pro...
Deming Chen, Jason Cong