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HPCA
2008
IEEE
16 years 5 months ago
Regional congestion awareness for load balance in networks-on-chip
Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in chip multiprocessors and system-on-chip designs. Existing interconnection networks use...
Paul Gratz, Boris Grot, Stephen W. Keckler
HPCA
2006
IEEE
16 years 5 months ago
Last level cache (LLC) performance of data mining workloads on a CMP - a case study of parallel bioinformatics workloads
With the continuing growth in the amount of genetic data, members of the bioinformatics community are developing a variety of data-mining applications to understand the data and d...
Aamer Jaleel, Matthew Mattina, Bruce L. Jacob
HPCA
2005
IEEE
16 years 5 months ago
Tapping ZettaRAMTM for Low-Power Memory Systems
ZettaRAMTM is a new memory technology under development by ZettaCoreTM as a potential replacement for conventional DRAM. The key innovation is replacing the conventional capacitor...
Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Eric Roten...
HPCA
2001
IEEE
16 years 5 months ago
Self-Tuned Congestion Control for Multiprocessor Networks
Network performance in tightly-coupled multiprocessors typically degrades rapidly beyond network saturation. Consequently, designers must keep a network below its saturation point...
Mithuna Thottethodi, Alvin R. Lebeck, Shubhendu S....
CHI
2003
ACM
16 years 5 months ago
Post-cognitivist HCI: second-wave theories
Historically, the dominant paradigm in HCI, when it appeared as a field in early 80s, was information processing ("cognitivist") psychology. In recent decades, as the fo...
Bonnie A. Nardi, Edwin Hutchins, James D. Hollan, ...