151 search results - page 10 / 31 » Bi-criteria Pipeline Mappings for Parallel Image Processing |
ICIP
2005
IEEE
15 years 11 months ago
2005
IEEE
This paper describes the architecture of an 8x8 2-D DCT/IDCT processor with high throughput, reduced hardware, and a parallel-pipeline scheme. This architecture allows the process...
CVPR
2007
IEEE
16 years 1 days ago
2007
IEEE
This paper presents our progress on OpenVL - a novel software architecture to address efficiency through facilitating hardware acceleration, reusability and scalability for comput...
ICIP
2003
IEEE
15 years 11 months ago
2003
IEEE
This paper describes a new co-processor architecture designed for CMOS sensor imaging. The co-processor unit is integrated into the image acquisition loop so as to exploit the ful...
DAGM
2010
Springer
14 years 11 months ago
2010
Springer
Abstract. We consider an automated processing pipeline for tissue micro array analysis (TMA) of renal cell carcinoma. It consists of several consecutive tasks, which can be mapped ...
IPPS
1999
IEEE
15 years 2 months ago
1999
IEEE
Abstract. This paper proposes a method for implementing fractal image compression on dynamically reconfigurable architecture. In the encoding of this compression, metric computatio...