Nanometer CMOS scaling has resulted in greatly increased circuit variability, with extremely adverse consequences on design predictability and yield. A number of recent works have...
Ashoka Visweswara Sathanur, Antonio Pullini, Luca ...
In practice, learning from data is often hampered by the limited training examples. In this paper, as the size of training data varies, we empirically investigate several probabil...
We show that currently prevalent practices for network path measurements can produce inaccurate inferences because of sampling biases. The inferred mean path latency can be more t...
With continued scaling into the sub-90nm regime, the role of process, voltage and temperature (PVT) variations on the performance of VLSI circuits has become extremely important. T...
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatneka...
If V is a set of n points in the unit square [0, 1]2 , and if R : V + is an assignment of positive real numbers (radii) to to those points, define a graph G(R) as follows: {v, w}...