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WCRE
2002
IEEE
15 years 7 months ago
Register Liveness Analysis for Optimizing Dynamic Binary Translation
Dynamic binary translators compile machine code from a source architecture to a target architecture at run time. Due to the hard time constraints of just-in-time compilation only ...
Mark Probst, Andreas Krall, Bernhard Scholz
CGO
2004
IEEE
15 years 6 months ago
The Accuracy of Initial Prediction in Two-Phase Dynamic Binary Translators
Dynamic binary translators use a two-phase approach to identify and optimize frequently executed code dynamically. In the first step (profiling phase), blocks of code are interpre...
Youfeng Wu, Mauricio Breternitz Jr., Justin Quek, ...
ICIP
2006
IEEE
16 years 4 months ago
Bit Rate Reduction of Vector Representation of Binary Images
Vector representation of binary images has an advantage of keeping high image quality for arbitrary scaling as well as editing capability of an object. However, the vector represe...
Yuki Yamamoto, Kei Kawamura, Hiroshi Watanabe
ISCAS
2005
IEEE
170views Hardware» more  ISCAS 2005»
15 years 8 months ago
Quantized LDPC decoder design for binary symmetric channels
Abstract— Binary Symmetric Channels (BSC) like the Interchip buses and the Intra-chip buses are gaining a lot of attention due to their widespread use with multimedia storage dev...
Rohit Singhal, Gwan S. Choi, Rabi N. Mahapatra
110
Voted
DAC
2005
ACM
15 years 4 months ago
Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility
In this paper we present the impact of dynamically translating any sequence of instructions into combinational logic. The proposed approach combines a reconfigurable architecture ...
Antonio Carlos Schneider Beck, Luigi Carro