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EURODAC
1994
IEEE
148views VHDL» more  EURODAC 1994»
15 years 10 months ago
BiTeS: a BDD based test pattern generator for strong robust path delay faults
This paper presents an algorithm for generation of test patterns for strong robust path delay faults, i.e. tests that propagate the fault along a single path and additionally are ...
Rolf Drechsler
ICC
2007
IEEE
150views Communications» more  ICC 2007»
15 years 10 months ago
ACE Spectrum of LDPC Codes and Generalized ACE Design
The construction of good, finite-length, LDPC codes is currently an attractive research area. Reducing attention to the Binary Erasure Channel (BEC), this problem translates into t...
Dejan Vukobratovic, Aleksandar Djurendic, Vojin Se...
ICASSP
2009
IEEE
15 years 10 months ago
A fast feature extraction method
A fast subspace analysis and feature extraction algorithm is proposed which is based on fast Haar transform and integral vector. In rapid object detection and conventional binary ...
Jing Pan, Yanwei Pang, Xuelong Li, Yuan Yuan, Dach...
CP
2006
Springer
15 years 9 months ago
Compiling Constraint Networks into AND/OR Multi-valued Decision Diagrams (AOMDDs)
Abstract. Inspired by AND/OR search spaces for graphical models recently introduced, we propose to augment Ordered Decision Diagrams with AND nodes, in order to capture function de...
Robert Mateescu, Rina Dechter
FUN
2010
Springer
219views Algorithms» more  FUN 2010»
15 years 9 months ago
The Magic of a Number System
We introduce a new number system that supports increments with a constant number of digit changes. We also give a simple method that extends any number system supporting increments...
Amr Elmasry, Claus Jensen, Jyrki Katajainen