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DFT
2002
IEEE
103views VLSI» more  DFT 2002»
15 years 9 months ago
Input Ordering in Concurrent Checkers to Reduce Power Consumption
A novel approach for reducing power consumption in checkers used for concurrent error detection is presented. Spatial correlations between the outputs of the circuit that drives t...
Kartik Mohanram, Nur A. Touba
DSD
2002
IEEE
93views Hardware» more  DSD 2002»
15 years 9 months ago
Fault Latencies of Concurrent Checking FSMs
In this paper we introduce concepts of a potential fault latency and a real fault latency for Finite State Machines (FSMs). The potential latency defines a minimal value of the po...
Roman Goot, Ilya Levin, Sergei Ostanin
152
Voted
IPPS
2002
IEEE
15 years 9 months ago
High-Performance Parallel and Distributed Computing for the BMI Eigenvalue Problem
The BMI Eigenvalue Problem is one of optimization problems and is to minimize the greatest eigenvalue of a bilinear matrix function. This paper proposes a parallel algorithm to co...
Kento Aida, Yoshiaki Futakata, Shinji Hara
127
Voted
ISMVL
2010
IEEE
174views Hardware» more  ISMVL 2010»
15 years 9 months ago
Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits
—Fixed-point multiplication architectures are designed and evaluated using a set of logic cells based on a radix-4, quaternary number system. The library of logic circuits is bas...
Satyendra R. Datla, Mitchell A. Thornton
COCOON
2010
Springer
15 years 9 months ago
Auspicious Tatami Mat Arrangements
The main purpose of this paper is to introduce the idea of tatami tilings, and to present some of the many interesting and fun questions that arise when studying them. Roughly spea...
Alejandro Erickson, Frank Ruskey, Mark Schurch, Je...