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Bit-Width Selection for Data-Path Implementations
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ISLPED
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Low-power high-level synthesis for FPGA architectures
15 years 10 months ago
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This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan
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