Sciweavers

166 search results - page 11 / 34
» Black-Box Randomized Reductions in Algorithmic Mechanism Des...
Sort
View
IPPS
2006
IEEE
15 years 5 months ago
Dynamic power saving in fat-tree interconnection networks using on/off links
Current trends in high-performance parallel computers show that fat-tree interconnection networks are one of the most popular topologies. The particular characteristics of this to...
Marina Alonso, Salvador Coll, Juan Miguel Mart&iac...
114
Voted
VLSID
2010
IEEE
211views VLSI» more  VLSID 2010»
15 years 3 months ago
A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM
A novel design approach for simultaneous power and stability (static noise margin, SNM) optimization of nanoCMOS static random access memory (SRAM) is presented. A 45nm single-end...
Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dh...
DAC
2008
ACM
16 years 23 days ago
On the role of timing masking in reliable logic circuit design
Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking ...
Smita Krishnaswamy, Igor L. Markov, John P. Hayes
CRYPTO
2003
Springer
124views Cryptology» more  CRYPTO 2003»
15 years 5 months ago
Primality Proving via One Round in ECPP and One Iteration in AKS
On August 2002, Agrawal, Kayal and Saxena announced the first deterministic and polynomial time primality testing algorithm. For an input n, the AKS algorithm runs in heuristic t...
Qi Cheng
ISVLSI
2003
IEEE
157views VLSI» more  ISVLSI 2003»
15 years 5 months ago
Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering
This paper describes a technique for re-ordering of scan cells to minimize power dissipation that is also capable of reducing the area overhead of the circuit compared to a random...
Shalini Ghosh, Sugato Basu, Nur A. Touba