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HVC
2005
Springer
183views Hardware» more  HVC 2005»
15 years 3 months ago
Detecting Potential Deadlocks with Static Analysis and Run-Time Monitoring
Concurrent programs are notorious for containing errors that are difficult to reproduce and diagnose. A common kind of concurrency error is deadlock, which occurs when a set of thr...
Rahul Agarwal, Liqiang Wang, Scott D. Stoller
66
Voted
WSC
2007
14 years 12 months ago
Agent-model validation based on historical data
Combat, unlike many real-world processes, tends to be singular in nature. That is, there are not multiple occurrences from which to hypothesize a probability distribution model of...
Lance E. Champagne, Raymond R. Hill
ICCAD
2006
IEEE
165views Hardware» more  ICCAD 2006»
15 years 6 months ago
A fast block structure preserving model order reduction for inverse inductance circuits
Most existing RCL−1 circuit reductions stamp inverse inductance L−1 elements by a second-order nodal analysis (NA). The NA formulation uses nodal voltage variables and describ...
Hao Yu, Yiyu Shi, Lei He, David Smart
TVLSI
2010
14 years 4 months ago
Fast Analysis of a Large-Scale Inductive Interconnect by Block-Structure-Preserved Macromodeling
To efficiently analyze the large-scale interconnect dominant circuits with inductive couplings (mutual inductances), this paper introduces a new state matrix, called VNA, to stamp ...
Hao Yu, Chunta Chu, Yiyu Shi, David Smart, Lei He,...
ISQED
2007
IEEE
151views Hardware» more  ISQED 2007»
15 years 3 months ago
Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations
We propose gate level statistical simulation to bridge the gap between the most accurate Monte Carlo SPICE simulation and the most efficient circuit level statistical static timi...
Bao Liu