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ASPDAC
2005
ACM
111views Hardware» more  ASPDAC 2005»
15 years 7 months ago
Wave-pipelined on-chip global interconnect
— A novel wave-pipelined global interconnect system is developed for reliable, high throughput, on-chip data communication. We argue that because there is only a single signal pr...
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
COMPSAC
2005
IEEE
15 years 7 months ago
A Low-Latency Checkpointing Scheme for Mobile Computing Systems
Fault-tolerant mobile computing systems have different requirements and restrictions, not taken into account by conventional distributed systems. This paper presents a coordinate...
Guohui Li, LihChyun Shu
DAC
2005
ACM
15 years 7 months ago
Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions
Variability of process parameters makes prediction of digital circuit timing characteristics an important and challenging problem in modern chip design. Recently, statistical stat...
Hongliang Chang, Vladimir Zolotov, Sambasivan Nara...
DAC
2005
ACM
15 years 7 months ago
Logic soft errors in sub-65nm technologies design and CAD challenges
Logic soft errors are radiation induced transient errors in sequential elements (flip-flops and latches) and combinational logic. Robust enterprise platforms in sub-65nm technolog...
Subhasish Mitra, Tanay Karnik, Norbert Seifert, Mi...
DAC
2005
ACM
15 years 7 months ago
Efficient and accurate gate sizing with piecewise convex delay models
We present an efficient and accurate gate sizing tool that employs a novel piecewise convex delay model, handling both rise and fall delays, for static CMOS gates. The delay model...
Hiran Tennakoon, Carl Sechen
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