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139
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EUROPAR
2010
Springer
15 years 5 months ago
Power-Efficient Spilling Techniques for Chip Multiprocessors
Abstract. Current trends in CMPs indicate that the core count will increase in the near future. One of the main performance limiters of these forthcoming microarchitectures is the ...
Enric Herrero, José González, Ramon ...
ASAP
2007
IEEE
153views Hardware» more  ASAP 2007»
15 years 5 months ago
Performance Evaluation of Adaptive Routing Algorithms for achieving Fault Tolerance in NoC Fabrics
Commercial designs are integrating from 10 to 100 embedded functional and storage blocks in a single system on chip (SoC) currently, and the number is likely to increase significa...
Haibo Zhu, Partha Pratim Pande, Cristian Grecu
IAT
2008
IEEE
15 years 5 months ago
Planning with iFALCON: Towards A Neural-Network-Based BDI Agent Architecture
This paper presents iFALCON, a model of BDI (beliefdesire-intention) agents that is fully realized as a selforganizing neural network architecture. Based on multichannel network m...
Budhitama Subagdja, Ah-Hwee Tan
143
Voted
AC
2008
Springer
15 years 5 months ago
Distributed Sparse Matrices for Very High Level Languages
Sparse matrices are first class objects in many VHLLs (very high level languages) used for scientific computing. They are a basic building block for various numerical and combinat...
John R. Gilbert, Steve Reinhardt, Viral Shah
170
Voted
ADHOC
2007
173views more  ADHOC 2007»
15 years 5 months ago
QoS multicast routing by using multiple paths/trees in wireless ad hoc networks
In this paper, we investigate the issues of QoS multicast routing in wireless ad hoc networks. Due to limited bandwidth of a wireless node, a QoS multicast call could often be blo...
Huayi Wu, Xiaohua Jia
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